The present invention relates generally to a time division switching system for signals on multi-channel calls.
When switching multi-channel calls at multiples of the basic bearer speed, or basic traffic unit of the ISDN (integrated services digital network), it is required that signals on an outgoing highway must appear in the same sequence as they appear on the incoming highway, a requirement known as "time slot sequence integrity". To meet this requirement, the phase of a frame on incoming highways is rendered coincident with the phase of a corresponding frame on outgoing highways using two time switch memories 304 and 305 as shown in FIG. 1. This prior art time division switching system comprises a write-in counter 310 which provides the timing of the whole system. This counter is reset in response to a signal from a frame detector 309 at the beginning of an incoming frame on incoming highway 301. To switch the time slots #2 and #3 of a multi-channel call (b, c) are switched to time slots #1 and #4, the output of the write-in counter 310 is applied as an address signal to time switch memories 304 and 305 to write in signals on multi-channel calls (b.sub.1, c.sub.1) and (b.sub.2 , c.sub.2) into the storage locations #2 and #3 of memories 304 and 305, respectively. Control circuit 320 writes in read address codes "2" and "3" into storage locations #1 and #4 of the control memory 321, respectively. To secure the time slot sequence integrity, control memory 321 must wait for the completion of write operation on a given frame before proceeding with the read operation of that given frame (see FIG. 2). However, the incoming and outgoing frames must be in phase alignment with each other in order to secure time slot sequence integrity. If multi-channel calls are handled by a switching system of a T.times.S.times.T (time-space-time switch) configuration in which the phase relationship between incoming and outgoing frames is predetermined, a memory such as first-in-first-out (FIFO) must be used as a frame aligner. This adds to hardware volume and complexity.